module ADD64
(input clock,
input ci,
input [63:0] ia,ib,
output reg [63:0]o,
output reg co

);
reg [63:0]mida,midb;
reg ci_i;
always@(posedge clock)
begin
    mida<=ia;
    midb<=ib;
    ci_i<=ci;
    {co,o}<=mida+midb+ci_i;

end

endmodule
